RISC-V subset core
A single-cycle then pipelined RV32I core is the strongest general-purpose portfolio artifact in digital design — it exercises ISA decoding, hazards and verification discipline.
Project ideas & portfolio
Build things that prove capability.
A guide to choosing portfolio projects for what they demonstrate — to interviewers, instructors and your future self.
Portfolio archetypes
Projects that read as evidence.
Each archetype below is chosen because of what it proves to a reviewer — not because it demos well. Full build guidance for these and 19 more lives in the FPGA project guide.
Digital oscilloscope front-end
ADC sampling into block RAM with triggering and UART streaming shows you can build measurement infrastructure, not just follow labs.
Camera-to-display pipeline
Streaming video with a live convolution filter proves throughput thinking: line buffers, memory bandwidth and real constraints.
Environmental logger with power budget
Low-power sleep cycles, I2C sensors and a documented battery-life calculation demonstrate product-grade firmware judgment.
PID motor controller
Closed-loop control with encoder feedback and safety cutoffs is instantly legible to interviewers in automotive, robotics and industrial domains.
Logic analyzer with trigger engine
Building your own lab tool — capture, triggers, host dump — signals the self-sufficiency teams look for in hardware hires.
What makes a portfolio credible
Evidence beats volume.
Finished > started
Two documented, demonstrated projects outweigh ten half-built repos.
Numbers included
Utilization, timing, power or throughput figures make claims verifiable.
Failures narrated
A “what went wrong” section signals real engineering, not tutorial-following.
Readable by strangers
Block diagram, interface table, build steps — a reviewer should get it in five minutes.
Ready to build capability?
Want your project reviewed before you show it?
A technical audit turns a good project into a compelling one: structure, documentation, demo plan and the questions interviewers will ask about it.
Best enquiry details
Include your current level, target outcome, timeline, board or FPGA details if any, and whether you need training, review or implementation support.